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Saini, Pushpa, Mehra, Rajesh (2012) A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits. International Journal of Advanced Computer Science and Applications, 3. doi:10.14569/ijacsa.2012.031026

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Reference TypeJournal (article/letter/editorial)
TitleA Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits
JournalInternational Journal of Advanced Computer Science and Applications
AuthorsSaini, PushpaAuthor
Mehra, RajeshAuthor
Year2012Volume3
PublisherThe Science and Information Organization
DOIdoi:10.14569/ijacsa.2012.031026Search in ResearchGate
Generate Citation Formats
Mindat Ref. ID10368921Long-form Identifiermindat:1:5:10368921:2
GUID0
Full ReferenceSaini, Pushpa, Mehra, Rajesh (2012) A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits. International Journal of Advanced Computer Science and Applications, 3. doi:10.14569/ijacsa.2012.031026
Plain TextSaini, Pushpa, Mehra, Rajesh (2012) A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits. International Journal of Advanced Computer Science and Applications, 3. doi:10.14569/ijacsa.2012.031026
In(n.d.) International Journal of Advanced Computer Science and Applications Vol. 3. The Science and Information Organization

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Saini, Pushpa, Mehra, Rajesh (2012) Leakage Power Reduction in CMOS VLSI Circuits. International Journal of Computer Applications, 55. 42-48 doi:10.5120/8778-2721
Govindarajulu, Salendra, Prasad, Dr.T.Jayachandra, , C.Sreelakshmi, , Chandrakala, , U.Thirumalesh (2011) Energy-Efficient, Noise-Tolerant CMOS Domino VLSI Circuits in VDSM Technology. International Journal of Advanced Computer Science and Applications, 2. doi:10.14569/ijacsa.2011.020417
VaraPrasadDone, Manikya, Panwar, Uday, Khare, Kavita (2014) An Algorithm for Leakage Power Reduction through IVC in CMOS VLSI Digital Circuits. International Journal of Computer Applications, 94. 24-28 doi:10.5120/16356-5740
S.Aswale, P., S. Chopade, S. (2013) Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits. International Journal of Computer Applications, 70. 16-24 doi:10.5120/12005-6866
LeelaRani, V., Madhavi Latha, M., Sai Ramesh, A. (2012) Galeorstack- A Novel Leakage Reduction Technique for Low Power VLSI Design. International Journal of Computer Applications, 48. 29-38 doi:10.5120/7370-0146
Gupta, Swati, mehra, Rajesh (2011) Reconfigurable Efficient Design of Viterbi Decoder for Wireless Communication Systems. International Journal of Advanced Computer Science and Applications, 2. doi:10.14569/ijacsa.2011.020720
Tauseef, Md., Sharma, Sudeep, Jain, Rita (2016) A Novel Leakage Reduction Technique for Ultra-low Power in VLSI Circuit. International Journal of Computer Applications, 148. 29-34 doi:10.5120/ijca2016911090
Alimoradi, Adel, Rostami, Pourya, Karami, Manoocheher (2018) Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits. International Journal of Computer Applications, 179. 39-43 doi:10.5120/ijca2018916476
D, Pushpa (2017) A Novel Unsupervised Abnormal Event Identification Mechanism for Analysis of Crowded Scene. International Journal of Advanced Computer Science and Applications, 8. doi:10.14569/ijacsa.2017.081055
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