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Pousia, S, Murugan, K (2021) VLSI Implementation Of High Speed Low Power Design Using Hybrid Power Gating Technique. IOP Conference Series: Materials Science and Engineering, 1084 (1) 12058pp. doi:10.1088/1757-899x/1084/1/012058

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Reference TypeJournal (article/letter/editorial)
TitleVLSI Implementation Of High Speed Low Power Design Using Hybrid Power Gating Technique
JournalIOP Conference Series: Materials Science and Engineering
AuthorsPousia, SAuthor
Murugan, KAuthor
Year2021 (March 1)Volume1084
Issue1
PublisherIOP Publishing
DOIdoi:10.1088/1757-899x/1084/1/012058Search in ResearchGate
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Mindat Ref. ID13303360Long-form Identifiermindat:1:5:13303360:3
GUID0
Full ReferencePousia, S, Murugan, K (2021) VLSI Implementation Of High Speed Low Power Design Using Hybrid Power Gating Technique. IOP Conference Series: Materials Science and Engineering, 1084 (1) 12058pp. doi:10.1088/1757-899x/1084/1/012058
Plain TextPousia, S, Murugan, K (2021) VLSI Implementation Of High Speed Low Power Design Using Hybrid Power Gating Technique. IOP Conference Series: Materials Science and Engineering, 1084 (1) 12058pp. doi:10.1088/1757-899x/1084/1/012058
In(2021, March) IOP Conference Series: Materials Science and Engineering Vol. 1084 (1) IOP Publishing

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