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Matrosova, A. Yu., Nikolaeva, E. A., Rumyantseva, E. V. (2013) Delay testable logical circuit design. Russian Physics Journal, 55 (11). 1370-1372 doi:10.1007/s11182-013-9969-8

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Reference TypeJournal (article/letter/editorial)
TitleDelay testable logical circuit design
JournalRussian Physics Journal
AuthorsMatrosova, A. Yu.Author
Nikolaeva, E. A.Author
Rumyantseva, E. V.Author
Year2013 (April)Volume55
Issue11
PublisherSpringer Science and Business Media LLC
DOIdoi:10.1007/s11182-013-9969-8Search in ResearchGate
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Mindat Ref. ID9035706Long-form Identifiermindat:1:5:9035706:4
GUID0
Full ReferenceMatrosova, A. Yu., Nikolaeva, E. A., Rumyantseva, E. V. (2013) Delay testable logical circuit design. Russian Physics Journal, 55 (11). 1370-1372 doi:10.1007/s11182-013-9969-8
Plain TextMatrosova, A. Yu., Nikolaeva, E. A., Rumyantseva, E. V. (2013) Delay testable logical circuit design. Russian Physics Journal, 55 (11). 1370-1372 doi:10.1007/s11182-013-9969-8
In(2013, April) Russian Physics Journal Vol. 55 (11) Springer Science and Business Media LLC

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